View source for EE2301

Introduction to Digital System Design, '''Fall 2014'''

== Announcements ==

* Please email [mailto:mriedel@umn.edu Marc] if you haven't been received his emails to the class.
* There will be no labs or discussions the first week of the semester.

== Organization ==

=== People ===

* Instructor: Prof. [[Marc Riedel]] ([mailto:mriedel@umn.edu mriedel@umn.edu])

* Teaching Assistants
** Jeffrey Adolf ([mailto:adolf017@umn.edu adolf017@umn.edu]) Lab Section 09, 10
** Han-Tai Shiao ([mailto:shiao003@umn.edu shiao003@umn.edu]) Lab Section 02, 03, 04 12
** Brandon Veber ([mailto:veber001@umn.edu veber001@umn.edu]) Lab Section 05, 06, 07, 11
** Tor Anderson ([mailto:and02440@umn.edu and02440@umn.edu]) Grading
** Luke Everson ([mailto:evers193@umn.edu evers193@umn.edu]) Grading
** Sangho Yun ([mailto:yunxx066@umn.edu yunxx066@umn.edu])  Grading

=== Lecture ===

* Tu. &amp; Th. 9:45am - 11:00am, AmundH B75

=== Discussions ===

* Discussion (Section 20): Th. 12:20 P.M. - 01:10 P.M., KHKH 2-26
* Discussion (Section 21): Th. 01:25 P.M. - 02:15 P.M., STSS 131
* Discussion (Section 22): Th. 02:30 P.M. - 03:20 P.M., STSS 530
* Discussion (Section 23): F. 11:15 A.M. - 12:05 P.M., STSS 33

=== Lab ===

* Lab (Section 02), M. 10:10 A.M. - 12:05 P.M., KHKH 2-178
* Lab (Section 03), M. 01:25 P.M. - 03:20 P.M., KHKH 2-178
* Lab (Section 04), M. 03:35 P.M. - 05:30 P.M., KHKH 2-178
* Lab (Section 05), Tu. 11:15 A.M. - 01:10 P.M., KHKH 2-178
* Lab (Section 06), Tu. 01:25 P.M. - 03:20 P.M., KHKH 2-178
* Lab (Section 07), Tu. 03:35 P.M. - 05:30 P.M., KHKH 2-178
* Lab (Section 09), F. 10:10 A.M. - 12:05 P.M., KHKH 2-178
* Lab (Section 10), W. 01:25 P.M. - 03:20 P.M., KHKH 2-178
* Lab (Section 11), Th. 04:40 P.M. - 06:35 P.M., KHKH 2-178
* Lab (Section 12), M. 08:00 A.M. - 09:55 A.M., KHKH 2-178

=== Office Hours ===

* Marc Riedel, KHKH EE/CSi 4-167: Tue. 12:00pm - 2:00pm
* Tor Anderson, KHKH 2-127: Thurs. 11:00am - 1:00pm
* Luke Everson, KHKH Lower Level Atrium Commons: Wed. (Table 5) & Fri. (Table 4) 11:00am - 12:00pm
* Sangho Yun, KHKH EE/Csi 4-149: Wed. 10:00am - 12:00pm
* Han-Tai Shiao, KHKH EE/CSi 6-110: Mon. 12:00pm - 1:00pm
* Brandon Veber, KHKH EE/CSi 2-178: Thurs. 3:30pm - 4:30pm

=== Text & Manuals ===

'''Text''':  ''Charles H. Roth'', Jr.,  and ''Larry Kinney'', '''Fundamentals of Logic Design''', 7th ed.

'''Lab Manual''':  The parts you need for the laboratory are available as a laboratory kit in the ECE stockroom.

=== Grading ===

* Homework: '''20%'''
** 8 homeworks (2.5% each)

* Laboratory: '''20%'''
** 8 experiments (2.5% each)
** For each experiment:
*** Attendance: '''10%''' 
*** Prelab: '''10%''' 
*** Report: '''60%''' 
*** Evaluation of Lab Work: '''20%''' 

* Midterm Exam 1 (Tu. Oct. 14, 9:45am - 11:00am, AmundH B75): '''15%'''	
* Midterm Exam 2 (Tu.. Nov. 25, 9:45am - 11:00am, AmundH B75): '''15%'''	
* Final Exam (Th. Dec. 18, 8:00am-10:00am, AmundH B75): '''30%'''

=== Policies ===

* Exams are open book/open notes, held in class. 
* Calculators, phones, computers, or any other electronic devices may not be used in the exams.
* There will be no make-up exams except for verifiable illness or incapacity, approved by the university.
* An incomplete grade will only be given when all but a small portion of the coursework is complete and the student is unable to finish because of verifiable illness or incapacity, approved by the university. See [http://www.fpd.finop.umn.edu/groups/senate/documents/policy/gradingpolicy.html University Senate Grading Policy]. 
* All work submitted for the course must be the sole work of the student.  Any student who copies from another or cheats in any manner will receive a 0 for that assignment/exam with the possibility of more severe punishment, such as receiving an 'F' for the course or expulsion.  See University Student Conduct Policies: http://regents.umn.edu/sites/regents.umn.edu/files/policies/Student_Conduct_Code.pdf.

== Description ==

The course introduces the students to the theory and th e practice of digital system design, covering topics such as Boolean algebra, logic gates, combinational logic, logic simplification, sequential logic, design of synchronous sequential logic, VHDL modeling, and design of logic circuits lab.

== Topics ==

* Number Systems (1 week)
* Introduction to Digital Logic (2 weeks)
** Gates
** Combinational Circuits
** Boolean Expressions
** Representation of Boolean Functions
*** Truth Tables
*** Two-Level Forms (AND/OR/NAND/NOR)
* Circuits for Arithmetic Operations (1 week)
** Design of a Ripple Adder
** Subtraction, Multiplication by a Scalar
* Timing Analysis (0.5 weeks)
* Reduced, Ordered Binary Decision Diagrams (0.5 weeks)
* Intro to Logic Minimization (1 weeks)
** Karnaugh maps
* Advanced to Logic Minimization (1 weeks)
** Quine-McCluskey Method
** Joint Minimization of Multiple Functions
* Hazards (0.5 weeks)
* Design with "Don't Cares" (0.5 weeks)
* Combinational Circuit Design (2 weeks)
** Combinational Logic Modules 
*** Multiplexers
*** Encoders/Decoders
*** Comparators
* Introduction to Sequential Circuits (2 weeks)
** Latches & Flip-flops	
*** S-R and D Latches
*** S-R, J-K, D, and T Flip-Flops
* Intro to Verilog (1 week)
* Sequential Circuit Design (3 weeks)
** State Graphs and Tables
** Sequential Logic Modules 
*** Shifters
*** Counters
*** Registers		
** State Machines
*** State Assignments
*** State Reduction
* More Verilog (1 week)

'''Final Exam'''

== Lecture Summaries==

[Recommended reading in brackets.]

=== 09/02/14 ===

* How EE2301 Fits Into ECE Curriculum
* Why Digital Design is Relevant
* Why Computers are Amazing
* Discussion of Grading and Course Organization
[Text 1.1]

=== 09/04/14 ===

All About Number Systems.
* Converting from base 10 to base x.
* Converting from base x to base 10.
* Converting from base x to base y.
* Converting between base 2, 8, and 16 (or any two bases where one is a power of the other)
* Fractional numbers.
* Converting fractional numbers between base 10 and base 2.
[Text 1.2, 1.4]

=== 09/09/14 ===

Binary Arithmetic
* Addition
* Multiplication
* Subtraction
* Intro Boolean Algebra
* Truth Table, Circuits, and Boolean Expressions

[Text 1.3, 2.1, 2.2, 2.3]

=== 09/11/14 ===

From Truth Tables to Circuits
* AND-OR (a.k.a. sum of products)
* OR-AND (a.k.a. product of sums)
[Text 4.2]

=== 09/16/14 ===

Boolean Algebra
* Basic Theorems
** Distributive Law / Factoring
** De Morgan's Law
** Uniting, Absorption, Elimination, and Consensus 
Exclusive OR
* Properties
* XNF Form (a.k.a. Reed-Mueller Form)
[Text 2.4, 2.4, 2.6, 2.7, 2.8, 3.1, 3.2, 3.3]

=== 09/18/14 ===

* Two-Level Forms
** AND-OR, NAND-NAND, OR-NAND, NOR-OR
** OR-AND, NOR-NOR, AND-NOR, NAND-AND
** AND-XOR (with no negations)
* Transforming and Simplifying Logic Circuits
[Text 7.3]

=== 09/23/14 ===

* Combinational vs. Sequential Circuits
* Acylic vs. Cyclic Circuits
* Timing Analysis
[[http://cctbio.ece.umn.edu/EE2301/ee2301-2014-fall-timing-analysis.ppt Slides], Text 8.3]

=== 09/25/14 ===
* Binary Decision Diagrams 
** [http://cctbio.ece.umn.edu/EE2301/ee2301-2014-fall-binary-decision-diagrams.ppt Slides] 
** [http://en.wikipedia.org/wiki/Binary_decision_diagram Reference Page] 
**[http://cctbio.ece.umn.edu/EE2301/bryant-symbolic-boolean-manipulation-with-ordered-binary-decision-diagrams.pdf Research Paper]

=== 09/30/14 ===

* Graphs, Parity Trees
* XOR Function of many variables
* XOR Function with AND/OR gates

=== 10/2/14 ===

Two-Level Logic Minimization
* Uniting and Absorption Laws
* K-Maps (Part I)
[Text 2.6, 5]

=== 10/7/14 ===

* K-Maps (Part II)
* Quine-McCluskey Method (Part I)
[Text 5, 6]

=== 10/9/14 ===

* Quine-McCluskey Method (Part II)
* Multiplexers
[Text 6, 9.2]

=== 10/16/14 ===

* Midterm

=== 10/21/14 ===

* Combinational vs. Sequential Circuits
* Synchronous Sequential Circuits
* Memory
* Clocks
* Ring Oscillator

[Text 13.4]

=== 10/23/14 ===

* Latches vs. Flip-Flops
* S-R Latch
* Gated D Latch
* Hazards
[Text 8.4, 11.1, 11.2, 11.3]

=== 10/28/14 ===

* Flip-Flops with Holds and Clears
* Registers 
** Shift Registers
** Parallel Load Registers
[Text 11.8, 12.1, 12.2, 12.4]

=== 10/30/14 ===

* Counters 
* Linear-Feedback Shift Registers
[Text 12.3], [http://en.wikipedia.org/wiki/Linear_feedback_shift_register Wikipedia Page]

=== 11/04/14 ===

* Special Presentation by Misha Burich: A Career in Digital Design

=== 11/06/14 ===

* Moore vs. Mealy Machines
* State Transition Graphs
* State Transition Diagrams 
[Text 14.1, 14.2, 14.3]

=== 11/11/14 ===

* Synthesizing FSMs with D Flip-Flops and JK Flip-Flops
* Elimination of Redundant States 
[Text 15.1, 15.2, 15.6]

=== 11/13/14 ===

* Sorting Networks, Part I, [http://cctbio.ece.umn.edu/EE2301/ee2301-2014-fall-sorting-networks.ppt Slides]

=== 11/18/14 ===

* Sorting Networks, Part II, [http://cctbio.ece.umn.edu/EE2301/ee2301-2014-fall-sorting-networks.ppt Slides]

=== 11/20/14 ===

* Intro to Hardware Description Languages
[http://web.mit.edu/6.111/www/f2007/handouts/L04.pdf MIT Slides]

=== 12/02/14 ===

* State Machine Designs with JK Flip-Flops
* Arithmetic Operations
[Text 12.5, 18.1]

=== 12/04/14 ===

* Algorithmic State Machines, [[Media:ee2301-2014-fall-asm.pdf | Slides]]
[Text 19]

=== 12/09/14 ===

* Ideas in Logic Synthesis, [http://cctbio.ece.umn.edu/EE2301/ee2301-2014-fall-logic-synthesis.ppt Slides]

== Labs ==

=== Lab Experiments ===

* 09/08 -- 09/12, [http://www.cctbio.ece.umn.edu/EE2301/EE2301-Lab-01.docx Lab 1], [http://www.cctbio.ece.umn.edu/EE2301/EE2301-Lab-01-Report.docx Report template], turn in Prelab 1
* 09/15 -- 09/19, [http://www.cctbio.ece.umn.edu/EE2301/EE2301-Lab-01.docx Lab 1], [http://www.cctbio.ece.umn.edu/EE2301/EE2301-Lab-01-Report.docx Report template]
* 09/22 -- 09/26, [http://www.cctbio.ece.umn.edu/EE2301/EE2301-Lab-02.docx Lab 2], [http://www.cctbio.ece.umn.edu/EE2301/EE2301-Lab-02-Report.docx Report template], turn in Report 1, Prelab 2
* 09/29 -- 10/03, [http://www.cctbio.ece.umn.edu/EE2301/EE2301-Lab-02.docx Lab 2], [http://www.cctbio.ece.umn.edu/EE2301/EE2301-Lab-02-Report.docx Report template]
* 10/06 -- 10/10, [[Media:Lab-03.docx | Lab 3]], [[Media:Lab-03-Report.docx | Report template]], turn in Report 2, Prelab 3
* 10/13 -- 10/17, [[Media:Lab-03.docx | Lab 3]], [[Media:Lab-03-Report.docx | Report template]]
* 10/20 -- 10/24, [[Media:Lab-04.docx | Lab 4]], [[Media:Lab-04-Report.docx | Report template]], turn in Report 3, Prelab 4
* 10/27 -- 10/31, [[Media:Lab-06.docx | Lab 6]], [[Media:Lab-06-Report.docx | Report template]], turn in Report 4, Prelab 6
* 11/03 -- 11/07, [[Media:Lab-05.docx | Lab 5]], [[Media:Lab-05-Report.docx | Report template]], turn in Report 6, Prelab 5
* 11/10 -- 11/14, [[Media:Lab-08.docx | Lab 8]], [[Media:Lab-08-Report.docx | Report template]], turn in Report 5, Prelab 8
* 11/17 -- 11/21, [[Media:Lab-08.docx | Lab 8]], [[Media:Lab-08-Report.docx | Report template]]
* 11/24 -- 11/28, no labs
* 12/01 -- 12/05, [[Media:Lab-08.docx | Lab 8]], [[Media:Lab-08-Report.docx | Report template]]

=== Lab Equipment ===

* [http://www.cctbio.ece.umn.edu/EE2301/EE2301-Lab-Appendix-A.doc Appendix A]
* [http://www.cctbio.ece.umn.edu/EE2301/EE2301-Lab-Appendix-B.doc Appendix B]
* [http://www.cctbio.ece.umn.edu/EE2301/EE2301-Lab-Appendix-C.doc Appendix C]

== Sample Problems  ==

* [[Media:ee2301-2014-fall-problems-01.pdf | Set 1]], [[Media:ee2301-2014-fall-problems-01-soln.txt | Solutions]]

== Homeworks ==

* [http://www.cctbio.ece.umn.edu/EE2301/ee2301-2014-fall-homework-01.pdf Homework 1]
* [http://www.cctbio.ece.umn.edu/EE2301/ee2301-2014-fall-homework-02.pdf Homework 2]
* [[Media:ee2301-2014-fall-homework-03.pdf | Homework 3]]
* [[Media:ee2301-2014-fall-homework-04.pdf | Homework 4]],
* [[Media:ee2301-2014-fall-homework-05.pdf | Homework 5]], 
* [[Media:ee2301-2014-fall-homework-06.pdf | Homework 6]]

== Exams ==

* [[Media:ee2301-2014-fall-exam-01.pdf | Midterm I]], [[Media:ee2301-2014-fall-exam-01-sol.pdf | Midterm I Solution]], [[Media:Prob5.m | Prob5_MATLAB_mfile]].
* [[Media:EE2301_Midterm2_sol_rev.pdf‎ | Midterm II Solution]]
* [[Media:EE2301_Final_sol.pdf‎ | Final Solution]]